Uniprocessor architecture

Von Neumann Architecture

The Von Neumann architecture has 3 main components - the ALU, the Control Unit, and the Memory Store. The ALU is where data is processed. To process the data, operations (instructions e.g. add) and operands (e.g. numbers) are needed. The ALU is controlled by the Control Unit - which selects and feeds in the information to the ALU at the correct time. The Control Unit knows when to send information to the ALU as it knows what the ALU's state is as the ALU feeds this information back to the Control Unit. Together, the ALU and Control Unit form the CPU.

Data is stored in memory. The big insight into Von Neumann architecture is that the data for instructions and the data for operands are stored in the same location. The Control Unit prompts the memory to send back operations (Fetch) (which is then sent to the ALU via the Control Lines (Decode and Execute)) and also prompts the memory to send operands directly to the ALU. The new processed data from the ALU is then sent back into the memory. If the data store and control unit work fast enough, the ALU can be kept in continuous operation. There are 2 types of memory store, sequential (e.g. magnetic tape) and random (e.g. RAM. The time to access the next address with sequential memory depends on the distance between the previous memory address and the current one (as the tape must rewind or fast forward) while for RAM the time does not depend on the previous fetch cycle.

Humans can interface with the computer using input and output devices or IO. These are connected to the Control Unit.

Von Neumann Bottleneck

As mentioned above, in order for the ALU to be in continuous operation, data must be fed into the ALU quickly. However, this is often not achieved - causing the ALU to spend much of the time waiting for the next instruction. This is often due to the fact that the shared memory that the Von Neumann architecture uses, also limits throughput (data transfer rate) between the memory and the CPU as instructions and data cannot be accessed at the same time. This problem becomes more severe with fast operations on large amounts of data.

There are 2 main ways to limit the Von Neumann Bottleneck, they are:

1. Alternative Architectures (e.g. Harvard Architecture)
2. Minimising use of main memory
   • Caching
   • Internal Registers

Harvard Architecture

Unlike the Von Neumann Architecture, Harvard Architecture does use separate memory stores for instructions and data. This allows the ALU and Control Unit to access the memory simultaneously. This increase in performance is offset by a decrease in flexibility (memory is also smaller). Therefore, it is only used in specialised hardware like microcontrollers and embedded systems (like an Arduino), or in processors that are programmed to utilise the simultaneous access to memory. Harvard Architecture has been modified over the years to improve its performance. These include providing a data pathway between the 2 storages, resulting in only 1 loading mechanism from store to CPU and having separate caching for data and instructions, but a single store - allowing a processor to function in Harvard or Von Neumann mode.

Caching

A cache is a small data store that is a duplicate of some parts of the main memory, but capable of more rapid access. Cache is also known as SRAM and the main memory is known as DRAM. There are 2 types of cache, L1 and L2. L1 cache is very close to the processor and provides very fast access, however it is rather small. L2 cache is just off the chip, and is slightly slower than L1, but has a larger store.

Registers

Registers provide the fastest access to the CPU and are used to store values that are used in ongoing computations. Registers are stored on the CPU. Most programming languages (exceptions include C and Assembly) do not allow direct access to the register.